1. Field of the Invention
The invention relates generally to delay circuits, and more particularly, to a delay circuit for delaying the supplied signal in response to the clock signal with high reliability.
2. Description of the Related Art
In the design of semi-customized LSI such as standard cells and gate arrays, computer aided design (hereinafter referred to as "CAD") is widely used. For example, a circuit block cell having standard features is previously prepared to be previously registered in a library under the standard cell method. With the CAD system, the desired circuit block cells are automatically arranged and wired in accordance with an automatic arrangement wiring program. In the execution of the automatic arrangement wiring program, the area for arrangement of the wiring is used as effectively as possible to minimize the occupying area of the circuit. As a result, it is seldom that the length of the wiring is designed to be minimum.
However, the delay caused by the wiring for connecting elements has recently evolved into a problem that cannot be ignored as the rapid operation of semiconductor integrated circuits advances. Under such a circumstance, the problem set forth hereinafter occurs when more than one master slave type flipflops are cascaded. In the following description, a delay type (hereinafter referred to as "D-type") flipflop is adopted as an example of a master slave type flipflop.
FIG. 8 is a simplified block diagram of a gate array. Referring to FIG. 8, the gate array comprises an input/output pad 30 for externally inputting/outputting signals, and base cell columns 31 and 32. Five D-type flipflops 91-95 are implemented using the base cell column. The five flipflops 91-95 are connected in cascade to each other by a wiring (not shown) to construct a shift register having five stages. The wiring path to interconnect each of the flipflops is determined by carrying out the automatic arrangement wiring program provided within the CAD system.
FIG. 9 is a circuit diagram of a conventional D-type flipflop. A D-type flipflop has the most simple circuit configuration among the numerous master slave type flipflops. Referring to FIG. 9, the D-type flipflop comprises inverters 2 and 3 forming the master latch, and inverters 6 and 7 forming the slave latch. A PMOS transistor 1 is connected for the purpose of input control of the master latch. For the output control of the master latch, a NMOS transistor 4 is connected. Transistors 1 and 4 operate in response to clock signal CK. Data D applied to the D-type flipflop is provided as the output data Q with a delay defined by the frequency of the clock signal CK.
FIG. 10 is a timing diagram for explaining the operation of the circuit shown in FIG. 9. In operation, input data D is sampled and held in the master latch formed by inverters 2 and 3 in response to the fall and subsequent rise of the clock signal CK. Since the transistor 4 is turned on in response to the high level of the clock signal CK, the data signal held within the master latch is provided to the slave latch formed by inverters 6 and 7. As a result, the output data signal Q is provided via the slave latch.
FIG. 11 is a circuit diagram showing the circuit connection when two D-type flipflops are cascaded. FIG. 12 is a timing diagram for explaining the operation. It should be noted in FIG. 12 that the clock signal CK2 applied to the flipflop 92 is delayed by .DELTA.t with respect to the clock signal CK1 applied to flipflop 91 by clock skew. This delay time .DELTA.t may be caused by arranging and wiring the two flipflops 9 and 92 in accordance with the automatic arrangement wiring program of the above mentioned CAD system. That is, the flipflop 92 is connected so as to receive the clock signal CK via a wiring W longer than the flipflop 91 to cause the delay time at called clock skew.